1. Field of the Invention
This invention relates to a process for the manufacture of a circuit for the electrical interconnection of semiconductor devices. More particularly, the invention relates to a process of the manufacture of a circuit having either a plurality of metal layers or for use in multi-chip modules.
2. Description of Related Art
Microelectronic devices such as silicon based semiconductor integrated circuits are encased in a housing to protect the fragile circuitry form mechanical or corrosive damage. One housing is formed by encasing the microelectronic device between a base and a cover. Alternatively, the housing may be a plastic resin molded around the device. An electrically conductive lead frame passes through the housing to transmit electrical signals between the device and external circuitry. Interconnection between the leadframe and input/output (I/O) pads on the microelectronic device is either by thin wire bonds or an interconnect tape.
One form of interconnect circuit, commonly referred to as TAB (for tape automated bonding) tape is formed into a plurality of individual sites. Each site defines a plurality of narrow leads arranged to extend outwardly from the integrated circuit device. The inner lead portions are bonded to I/O pads on a surface of the device. The outer lead portions are bonded to a leadframe, circuit board or other external circuitry.
TAB tape is provided in several formats. A single layer tape has an all metal construction. A two layer construction has a metal layer supported by a dielectric backing layer. A three layer construction has a metal layer adhesively bonded to a dielectric support layer. The dielectric support layer is typically a polyimide such as KAPTON manufactured by DuPont. The thickness of the dielectric support layer ranges from about 2 mils up to about 5 mils.
The metal foil layer is usually copper or a dilute copper alloy having a thickness of from about 1/2 to 6 mils. Leads are patterned in the foil by photolithography. Lead widths as thin as 2 mils are commercially produced. The use of copper or a dilute copper alloy provides high electrical conductivity.
U.S. Pat. No. 4,982,495 to Okimoto et al discloses one manufacturing process for a three layer TAB tape. An adhesive is coated on a polyimide film. Sprocket holes and a personality window are punched through both the adhesive and the polyimide film. A copper foil is laminated to the adhesive and then a lead pattern is formed in the copper by photolithography.
One problem with this method is a separate punch tool is needed for each site configuration. The punch stamps through the polyimide and adhesive to define the personality window and sprocket holes used to guide the TAB tape through the remaining assembly procedures and bonding to the microelectronic device. While the tooling costs may be amortized over an extended production run, the costs are often prohibitive for a specialized site configuration or for evaluation of a tape design.
One way to reduce the cost of manufacturing a tape configuration and to reduce the time necessary to transfer a circuit design to the polyimide supported tape is by etching the sprocket holes and personality window in the polyimide and adhesive. This technique has met with minimal success because polyimide is soluble in concentrated alkaline solutions such as potassium hydroxide or sodium hydroxide and most conventional adhesives are soluble in concentrated acids such as sulfuric acid or organic solvents such as methylethyl ketone.
Immersion in two separate etching solutions, such as a hydroxide followed by an acid is one solution. This approach is not economical and has the difficulty of identifying a masking compound which is chemically resistant to both solutions and readily removed subsequent to etching.
The manufacture of small quantities of interconnect tape becomes even more difficult when complex configurations are required. One such configuration is a multi-metal layer tape as disclosed in U.S. Pat. No. 5,025,114 to Braden and 5,065,228 to Foster et al, both of which are incorporated by reference herein in their entireties. The '114 patent discloses an interposer circuit. The interposer is disposed between a semiconductor device and a leadframe to reduce the length of the lead wires. Shorter length lead wires permit the use of faster operating speeds and reduce the possibility of an electrical short circuit due to lead wire sweep.
The '228 patent discloses a TAB circuit having at least two separate metal layers. One metal layer is formed into ground and/or signal circuits while the other is formed into signal circuits. This structure is commonly referred to as a GTAB.
Another customized circuit is for electrically interconnecting a plurality of integrated circuit devices on a single substrate. A package encasing this configuration is known as a multi chip module (MCM). The circuit electrically interconnects one device to another as well as the devices to a lead frame or other external circuitry. Both the circuit pattern and the positioning of the personality windows must be configured for each specific design. Separate stamping tools for each MCM is a costly option.
There exists, therefore, a need for a process to inexpensively manufacture small quantities of customized interconnect circuits which does not have the disadvantages of the prior art.